Memory Maps
Table 5-13. Two-Channel TPM detailed memory map
Address
Register
Bit 7
6
5
4
3
2
1
Bit 0
(FF)FF_8120
TPM_SC
TOF
TOIE
CPWMS
CLKS
PS
(FF)FF_8121
(FF)FF_8122
(FF)FF_8123
(FF)FF_8124
(FF)FF_8125
(FF)FF_8126
(FF)FF_8127
(FF)FF_8128
(FF)FF_8129
(FF)FF_812A
TPM_CNTH
TPM_CNTL
TPM_MODH
TPM_MODL
TPM_C0SC
TPM_C0VH
TPM_C0VL
TPM_C1SC
TPM_C1VH
TPM_C1VL
Bit 15
Bit 7
Bit 15
Bit 7
CH0F
Bit 15
Bit 7
CH1F
Bit 15
Bit 7
14
6
14
6
CH0IE
14
6
CH1IE
14
6
13
5
13
5
MS0B
13
5
MS1B
13
5
12
4
12
4
MS0A
12
4
MS1A
12
4
11
3
11
3
ELS0B
11
3
ELS1B
11
3
10
2
10
2
ELS0A
10
2
ELS1A
10
2
9
1
9
1
0
9
1
0
9
1
Bit 8
Bit 0
Bit 8
Bit 0
0
Bit 8
Bit 0
0
Bit 8
Bit 0
Table 5-14. Programmable Delay Block (PDB) detailed memory map
Address
(FF)FF_EC00
Register
PDB_SCR
Bit 7
6
PRESCALER
5
4
SB
3
SA
2
IENB
1
IENA
Bit 0
BOS[1]
BOS[0]
AOS
CONT
SWTRI
G
TRIGSEL
EN
(FF)FF_EC02
(FF)FF_EC04
(FF)FF_EC06
(FF)FF_EC08
PDB_DELAYA
PDB_DELAYB
PDB_MOD
PDB_COUNT
DELAYA[15:8]
DELAYA[7:0]
DELAYB[15:8]
DELAYB[7:0]
MOD[15:8]
MOD[7:0]
COUNT[15:8]
COUNT[7:0]
NOTE
The Flash Controller registers may only be accessed when the CPU is in
Supervisor mode.
NOTE
The AFE registers may only be accessed when the CPU is in Supervisor
mode.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
55
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